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riscv: keep mstatus.MPP=M after mret on harts without U-mode - #2396

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riscv: keep mstatus.MPP=M after mret on harts without U-mode#2396
carlosqwqqwq wants to merge 2 commits into
unicorn-engine:devfrom
carlosqwqqwq:fix/riscv-mret-mpp-no-u

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@carlosqwqqwq

@carlosqwqqwq carlosqwqqwq commented Aug 12, 2026

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Fixes #2391

Problem

helper_mret unconditionally writes mstatus.MPP = PRV_U. On a hart whose MISA does not include U, the least-privileged supported mode is M, so after mret the MPP field must read 3, not 0. The reproducer runs on a locally built no-U model library (default riscv_any with RVU cleared; stock E51/U54 keep U as the control).

Change

qemu/target/riscv/op_helper.c helper_mret selects PRV_U only when RVU is present and PRV_M otherwise. The focused unit test is test_riscv64_mret_without_u in tests/unit/test_riscv.c.

Validation

  • Rebased onto dev and built the RISC-V targets.
  • The public u034 suite includes the U-clear profile patch and an explicit U-enabled control.
  • The no-U witness reads back MPP=M; U-enabled behavior remains unchanged.

Public reproducer and explicit profile setup:
https://github.com/carlosqwqqwq/unicorn-riscv-repros/tree/main/u034

@carlosqwqqwq
carlosqwqqwq force-pushed the fix/riscv-mret-mpp-no-u branch from 893ccf9 to d7dd352 Compare August 29, 2026 07:25
@carlosqwqqwq
carlosqwqqwq changed the base branch from master to dev August 29, 2026 07:27
@carlosqwqqwq

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Thank you very much for taking the time to review this PR. We have rebased it onto dev and updated the mret MPP handling for harts without U-mode, with focused validation of the affected behavior. Could you please let us know what further code, test, or PR changes you would recommend? We will gladly adjust the patch to match the project guidelines.

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RISC-V: mret sets mstatus.MPP=U on harts without U-mode

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